Flash memory devices have found growing commercial success in the electronic device market due in part to the ability of flash memory devices to store electronic data over long periods of time without an electric power supply. Additionally, flash memory devices can be erased and programmed over multiple write cycles after they have been installed in an electronic device. This combined functionality is especially useful in electronic device applications such as cellular telephones, personal digital assistants, computer BIOS storage, etc., where power supply is intermittent and programmability and data retention are desired.
Flash memory technology evolved from electrically erasable read only memory (EEPROM) chip technology, which can be erased in situ. Unlike dynamic random access memory (DRAM) devices and static random memory (SRAM) devices in which a single byte can be erased, flash memory devices are typically erased in fixed multi-bit blocks or sectors.
One type of flash memory device is constructed in a cell structure wherein a single bit of information is stored in each cell. FIG. 1 is a cross section view of an exemplary flash memory device. Memory device 100 is comprised of a substrate 101 having a source region 102 and a drain region 103. Typically, substrate 101 is a crystalline silicon semiconductor substrate which has undergone an N-type (electron rich) doping in source region 102 and drain region 103. Memory device 100 further comprises a gate array 104, also referred to as a “stack gate array.” In the embodiment of FIG. 1, gate array 104 is comprised of a tunnel oxide layer 105, a floating gate 106, and insulating layer 107, and a control gate 108. A channel region 109 underlies gate array 104 between source region 102 and drain region 103.
The single bit stacked gate flash memory cell (e.g., memory cell 100 of FIG. 1) is typically programmed by “channel hot electron injection” in which a high positive voltage is applied to control gate 108, source 102 is coupled to ground and drain 103 is coupled to a positive voltage. The resulting high electric field across the channel region accelerates electrons toward the drain region and imparts enough energy for them to become hot electrons. The hot electrons are scattered (e.g., by impurities or the substrate lattice structure of the substrate in the channel region) and are redirected toward the floating gate by the vertical field established by the positive control gate voltage. If the electrons have enough energy, they can tunnel through gate oxide 105 into floating gate 106 and become trapped there. This changes the threshold voltage VT, and thereby the channel conductance, of memory cell 100.
Memory cell 100 is read by connecting the source region 102 to ground, raising the voltage at the control gate 108 to the sense level and connecting the drain region 103 to a sense amplifier; if memory cell 100 is programmed, no current flows to the sense amplifier.
In order to erase memory cell 100, a voltage (e.g., 9 to 11 volts) is applied to the P-well 102, control gate 108 is held at a negative potential, and drain region 103 is allowed to float. Under these conditions, an electrical field is developed across tunnel oxide 105 between floating gate 106 and P-well 101. The electrons that are trapped in floating gate 106 flow toward and cluster at the portion of floating gate 106 overlying P-well 102.
In a typical manufacturing process, gate array 104 is fabricated by depositing successive layers of materials and performing a photolithographic etch through these layers down to the level of substrate 101. Frequently, this etching step results in damage to the tunnel oxide layer 105. For example, reaction between tunnel oxide layer 105 and the etchant may cause a degradation of the edge of the tunnel oxide layer such that it takes on a concave profile. Additionally, there may be some degradation at the junction of the tunnel oxide layer and the polysilicon of floating gate layer 106 such that the polysilicon layer is undercut.
In a conventional manufacturing process, lost or damaged tunnel oxide material is rebuilt during a re-oxidation process. Typically this involves placing the memory device in a furnace to induce a reaction between the material of tunnel oxide layer 105 and either dry oxygen or water vapor. During the course of the oxidation process, oxygen or water molecules diffuse into tunnel oxide layer 105 which expands the volume of the tunnel oxide material and thus rebuild the damaged tunnel oxide layer. Additionally, the oxygen or water molecules diffuse into the polysilicon of floating gate 106 and/or the silicon of substrate 101. As a result, the a portion of the junction between tunnel oxide layer 105 and floating gate layer 106 and/or substrate 101 becomes oxidized. FIG. 2 shows a section view of an exemplary flash memory device 200 that has been repaired using a conventional oxidation process. As shown in FIG. 2, tunnel oxide layer 105 extends into a portion of floating gate layer 106 and into a portion of substrate 101. This is not problematic in that the gate array 104 has a sufficient gate length (e.g., gate length 210) such that there is a portion of the tunnel oxide layer 105 (e.g., region 230 of FIG. 2) that has a uniform thickness.
Current technology trends are creating increasingly compact semiconductor structures in order to increase circuit density and to improve performance. One technique manufacturers use to scale down the size of semiconductor devices is to decrease the gate length of gate array 104. However, in memory devices having reduced gate lengths (e.g., 0.21μ–0.14μ), conventional methods for repairing damage to the tunnel oxide layer are proving disadvantageous.
FIG. 3 shows a section view of a prior art flash memory device 300 having a short channel length (e.g., less than 0.21μ). Due to the reduced gate length of gate array 104, oxidation of floating gate layer 106 and/or substrate 101 extends further into the interior of the gate array. Thus, in flash memory device 300, tunnel oxide layer 105 has a non-uniform profile. A non-uniform tunnel oxide layer is problematic when erasing a charge from insulating layer 107. As discussed above, in an erase operation, electrons are forced from insulating layer 107 into the channel region of substrate 101 (e.g., channel 109 of FIG. 1) underlying gate array 104 using Fowler-Nordheim tunneling. However, when tunnel oxide layer 105 has a non-uniform profile, as in FIG. 3, the erase voltage threshold (VTE) distribution becomes much wider. This can result in a phenomenon known as “overerase”. Once overerased, a flash memory cell cannot be programmed or read again within practical limits because of excessive memory transistor source-drain current, which grounds the bit line read or programming voltage.
Additionally, the oxidation process to repair damage to tunnel oxide layer 105 may occur after dopants have been implanted into source region 102 and drain region 103. Conventional methods for repairing damage to tunnel oxide layer 105 may result in what is known as “short channel effects” in memory devices having reduced gate length dimensions. For example, a conventional oxidation process may comprise placing memory device 100 in a furnace for 5–10 minutes and reach a peak processing temperature of approximately 900° C. However, this may also result in the dopants in source region 102 and drain region 103 to diffuse farther into channel region 109. As a result, undesirable short-channel characteristics may be exhibited. In short-channel devices, as the drain bias is increased, the drain depletion region widens into the channel and can merge with the source depletion region. This results in punch-through leakage between the source and drain and loss of gate control over the device.
This encroachment of the depletion region from the drain into the channel is known as Drain Induced Barrier Lowering (DIBL). The increase in leakage current associated with DIBL is especially problematic in flash memory devices as they are widely used in very low power applications, for example in mobile phones, due to the ability of flash memory to retain information without applied power. Increases in leakage current may have a significant deleterious effect on total power consumption of the product using the flash device. Furthermore, as DIBL increases, it becomes increasingly difficult to program the memory cell. Therefore, controlling DIBL is becoming increasingly important as the scale of flash memory devices decreases.
Thus, prior art methods for repairing damage to tunnel oxide layers are disadvantageous in that they may result in a non-uniform profile of the tunnel oxide layer in flash memory devices with a reduced gate length. This may cause difficulties in programming and/or erasing of flash memory cells. Additionally, they may result in more pronounced short channel effects in memory devices with a reduced gate length which may result in greater power consumption of the flash memory device and/or difficulty in programming the flash memory cells.